@MISC{GFACIRC1.MIZ,
  AUTHOR = {Yamaguchi, Shin'nosuke and Wasaki, Katsumi and Shimoi, Nobuhiro},
  TITLE = {Generalized Full Adder Circuits (GFAs). {P}art {I}},
  SECTION1 = {Preliminaries},
  SECTION2 = {Generalized Full Adder (GFA) Circuit (TYPE-0)},
  SECTION3 = {Generalized Full Adder (GFA) Circuit (TYPE-1)},
  SECTION4 = {Generalized Full Adder (GFA) Circuit (TYPE-2)},
  SECTION5 = {Generalized Full Adder (GFA) Circuit (TYPE-3)},
  DAY = {7},
  MONTH = {December},
  YEAR = {2005},
  ADDRESS1 = {Kyushu Institute of Technology\\Fukuoka},
  ADDRESS2 = {Shinshu University\\Nagano},
  ADDRESS3 = {Tokyo National College of Technology\\Tokyo},
  SUMMARY = {We formalize the concept of the Generalized Full Addition
and Subtraction circuits (GFAs), define the structures of calculation
units for the redundant signed digit (RSD) operations, and prove the 
stability of the circuits. Generally, one-bit binary full adder assumes
positive weights to all of its three binary inputs and two outputs.
We obtain four type of 1-bit GFA to constract the RSD arithmetic logical
units that we generalize full adder to have both positive and negative
weights to inputs and outputs.}}
