@MISC{FACIRC_2.MIZ,
  AUTHOR = {Bancerek, Grzegorz and Yamaguchi, Shin'nosuke and Wasaki, Katsumi},
  TITLE = {Full Adder Circuit. {P}art {II}},
  DAY = {22},
  MONTH = {March},
  YEAR = {2002},
  ADDRESS1 = {Bia{\l}ystok Technical University},
  ADDRESS2 = {Shinshu University\\Nagano},
  ADDRESS3 = {Shinshu University\\Nagano},
  SUMMARY = {In this article we continue the investigations from \cite{FACIRC_1.ABS} of verification of
a design of adder circuit.
We define it as a combination of 1-bit adders using schemes from \cite{CIRCCMB2.ABS}.
 $n$-bit adder circuit has the following structure\\
 \input FACIRC_2.PIC
As the main result we prove the stability of the circuit. Further works 
will consist of the proof of full correctness of the circuit.}}

