@MISC{GATE_5.MIZ,
  AUTHOR = {Yamazaki, Hiroshi and Wasaki, Katsumi},
  TITLE = {The Correctness of the High Speed Array Multiplier Circuits},
  SECTION1 = {Preliminaries},
  SECTION2 = {Logical Equivalence of Wallace Tree Multiplier},
  DAY = {28},
  MONTH = {August},
  YEAR = {2000},
  ADDRESS1 = {Shinshu University\\Nagano},
  ADDRESS2 = {Shinshu University\\Nagano},
  SUMMARY = {This article introduces the verification of the correctness for
the operations and the specification of the high speed array
multiplier. We formalize the concepts of 2-by-2 and 3-by-3 bit Plain
array multiplier, 3-by-3 Wallace tree multiplier circuit, and show
that outputs of the array multiplier are equivalent to outputs of
normal (sequencial) multiplier.}}

