reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th11:
  Gen w,y & u,u are_Ort_wrt w,y implies u = 0.V
proof
A1: now
    let a such that
A2: a<>0;
    0 < a implies 0 < a*a by XREAL_1:129;
    hence 0 < a*a by A2,XREAL_1:130;
  end;
  assume that
A3: Gen w,y and
A4: u,u are_Ort_wrt w,y;
  consider a1,a2,b1,b2 such that
A5: u = a1*w + a2*y and
A6: u = b1*w + b2*y and
A7: a1*b1 + a2*b2 = 0 by A4;
A8: a1=b1 & a2=b2 by A3,A5,A6,Lm4;
A9: a2 = 0
  proof
    assume a2<>0;
    then 0 < a2*a2 by A1;
    hence contradiction by A7,A8,XREAL_1:29,63;
  end;
  a1 = 0
  proof
    assume a1<>0;
    then 0 < a1*a1 by A1;
    hence contradiction by A7,A8,XREAL_1:29,63;
  end;
  hence u = 0*w + 0.V by A5,A9,RLVECT_1:10
    .= 0*w by RLVECT_1:4
    .= 0.V by RLVECT_1:10;
end;
