reserve s, s1, s2 for State of SCM+FSA,
  p, p1 for Instruction-Sequence of SCM+FSA,
  a, b for Int-Location,
  d for read-write Int-Location,
  f for FinSeq-Location,
  I for MacroInstruction of SCM+FSA,
  J for good MacroInstruction of SCM+FSA,
  k, m for Nat;

theorem Th7:
  s.intloc 0 = 1 or a is read-write implies StepTimes(a,J,p,s).0.(
  1-stRWNotIn ({a} \/ UsedILoc J)) = s.a
proof
  set I = J;
  set ST = StepTimes(a,I,p,s);
  set au = 1-stRWNotIn({a} \/ UsedILoc I);
  set Is = Initialized s;
  assume
A1: s.intloc 0 = 1 or a is read-write;
A2: a = intloc 0 or a is read-write by SCMFSA_M:def 2;
  thus ST.0.au = Exec(au := a, Is).au by SCMFSA_9:def 5
    .= Is.a by SCMFSA_2:63
    .= s.a by A1,A2,SCMFSA_M:9,37;
end;
