reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th13:
  Gen w,y & u <> 0.V implies ex a st v - a*u,u are_Ort_wrt w,y
proof
  assume that
A1: Gen w,y and
A2: u <> 0.V;
  consider a1,a2 such that
A3: u = a1*w + a2*y by A1;
  consider b1,b2 such that
A4: v = b1*w + b2*y by A1;
  set a = (b1*a1 + b2*a2)*(a1*a1 + a2*a2)";
  a*u = (a*a1)*w + (a*a2)*y by A3,Lm3;
  then
A5: v - a*u = (b1-a*a1)*w + (b2-a*a2)*y by A4,Lm1;
A6: (b1-a*a1)*a1 + (b2-a*a2)*a2 = (a1*b1 + a2*b2) + (-1)*(a1*(a*a1) + a2*(a
  *a2));
A7: a1*a1 + a2*a2 <> 0 by A1,A2,Th11,A3,Def2;
  (-1)*(a1*(a*a1) + a2*(a*a2)) = (-1)*((b1*a1 + b2*a2)*((a1*a1 + a2*a2)"*
  (a1*a1 + a2*a2)))
    .= (-1)*((b1*a1 + b2*a2)*1) by A7,XCMPLX_0:def 7
    .= -(a1*b1 + a2*b2);
  then v - a*u,u are_Ort_wrt w,y by A3,A5,A6;
  hence thesis;
end;
