reserve V for RealLinearSpace;
reserve x,y for VECTOR of V;
reserve AS for Oriented_Orthogonality_Space;
reserve u,u1,u2,u3,v,v1,v2,v3,w,w1 for Element of AS;

theorem Th13:
  Gen x,y & AS=CESpace(V,x,y) implies AS is Euclidean_like
  left_transitive right_transitive bach_transitive
proof
  assume that
A1: Gen x,y and
A2: AS=CESpace(V,x,y);
A3: CESpace(V,x,y)=OrtStr (# the carrier of V,CORTE(V,x,y) #) by
ANALORT:def 7;
A4: now
    let u,u1,u2,v,v1,v2,w,w1 be Element of AS;
    thus u,u1 '//' v,v1 & v,v1 '//' w,w1 & u2,v2 '//' w,w1 implies (w=w1 or v=
    v1 or u,u1 '//' u2,v2 )
    proof
      reconsider u9=u,v9=v,w9=w,u19=u1,v19=v1,w19=w1,u29=u2,v29=v2 as Element
      of V by A2,A3;
      u9,u19,v9,v19 are_COrte_wrt x,y & v9,v19,w9,w19 are_COrte_wrt x,y &
u29,v29,w9,w19 are_COrte_wrt x,y implies (w9=w19 or v9=v19 or u9,u19,u29,v29
      are_COrte_wrt x,y) by A1,ANALORT:44;
      hence thesis by A2,ANALORT:54;
    end;
  end;
A5: now
    let u,u1,v,v1 be Element of AS;
    thus u,u1 '//' v,v1 implies v,v1 '//' u1,u
    proof
      reconsider u9=u,v9=v,u19=u1,v19=v1 as Element of V by A2,A3;
      u9,u19,v9,v19 are_COrte_wrt x,y implies v9,v19,u19,u9 are_COrte_wrt
      x,y by A1,ANALORT:18;
      hence thesis by A2,ANALORT:54;
    end;
  end;
A6: now
    let u,u1,u2,v,v1,v2,w,w1 be Element of AS;
    thus u,u1 '//' v,v1 & v,v1 '//' w,w1 & u,u1 '//' u2,v2 implies (u=u1 or v=
    v1 or u2,v2 '//' w,w1 )
    proof
      reconsider u9=u,v9=v,w9=w,u19=u1,v19=v1,w19=w1,u29=u2,v29=v2 as Element
      of V by A2,A3;
      u9,u19,v9,v19 are_COrte_wrt x,y & v9,v19,w9,w19 are_COrte_wrt x,y &
u9,u19,u29,v29 are_COrte_wrt x,y implies (u9=u19 or v9=v19 or u29,v29,w9,w19
      are_COrte_wrt x,y) by A1,ANALORT:46;
      hence thesis by A2,ANALORT:54;
    end;
  end;
  now
    let u,u1,u2,v,v1,v2,w,w1 be Element of AS;
    thus u,u1 '//' v,v1 & w,w1 '//' v,v1 & w,w1 '//' u2,v2 implies (w=w1 or v=
    v1 or u,u1 '//' u2,v2 )
    proof
      reconsider u9=u,v9=v,w9=w,u19=u1,v19=v1,w19=w1,u29=u2,v29=v2 as Element
      of V by A2,A3;
      u9,u19,v9,v19 are_COrte_wrt x,y & w9,w19,v9,v19 are_COrte_wrt x,y &
w9,w19,u29,v29 are_COrte_wrt x,y implies (w9=w19 or v9=v19 or u9,u19,u29,v29
      are_COrte_wrt x,y) by A1,ANALORT:42;
      hence thesis by A2,ANALORT:54;
    end;
  end;
  hence thesis by A4,A6,A5;
end;
