reserve N for with_zero set;

theorem
  for A being standard IC-Ins-separated non empty
  with_non-empty_values AMI-Struct over N, I being Instruction of A st I is
  sequential holds not IC A in Out_\_Inp I
proof
  let A be standard IC-Ins-separated non empty
  with_non-empty_values AMI-Struct over N, I be Instruction of A;
  set t = the State of A;
  set l = IC A;
   reconsider sICt = IC t + 1 as Element of NAT;
   reconsider w = sICt as Element of Values l by MEMSTR_0:def 6;
  set s = t +* (l,w);
  assume for s being State of A holds Exec(I,s).IC A = IC s + 1;
  then
A1: Exec(I,t).l = IC t + 1 & Exec(I,s).l = IC s + 1;
  dom t = the carrier of A by PARTFUN1:def 2;
  then s.l = w by FUNCT_7:31;
  then Exec(I,t) <> Exec(I,s) by A1,NAT_1:16;
  hence thesis by Def4;
end;
