reserve Values for Values_with_Bool;
reserve a, a1, a2 for Element of the carrier of Values;
reserve S for Events_structure over Values;
reserve p, p1, p2 for Process of S;
reserve x, x1, x2 for Location of S;
reserve tr, tr1, tr2 for trace of S;
reserve e, e0, e1, e2, e3, e4, e5 for Event of S;
reserve E for EventSet of S;
reserve DS for DistributedSysWithSharedMem of Values;
reserve p, p1, p2 for Process of DS;
reserve x, x1, x2, flag1, flag2, turn for Location of DS;
reserve tr, tr1, tr2 for trace of DS;
reserve e, e0, e1, e2, e3, e4, e5 for Event of DS;
reserve E for EventSet of DS;

theorem lemwbefr:
  e1 in tr & e2 in tr &
  e1 reads x,a1 & e2 reads x,a2 & e1<=e2 & a1<>a2
implies
  ex e st
    e in tr & e1 << e & e << e2 & e writesto x,a2
proof
  assume A0: e1 in tr & e2 in tr;
  assume A1: e1 reads x,a1 & e2 reads x,a2 & e1<=e2 & a1<>a2;
  DS is consistent;
  then DS is rw-consistent;
  then consider e2w being Event of DS such that
  B1: e2w in tr & e2w < e2 & e2w writesto x & val e2w = a2 &
      for e st e in tr & e <= e2 & e writesto x
      holds e <= e2w by A0,A1;
  DS is consistent;
  then JJ0: DS is rw-ordered;
  C1: not e2w << e1
  proof
    assume D1: e2w << e1;
    DS is consistent;
    then DS is rw-consistent;
    then consider e1w being Event of DS such that
    D2: e1w in tr & e1w < e1 & e1w writesto x & val e1w = a1 &
      for e st e in tr & e <= e1 & e writesto x
      holds e <= e1w by A0,A1;
    D3: e2w <= e1w by D1,D2,B1;
    e1w <= e1 & e1 <= e2 by A1, D2, ORDERS_2:def 6;
    then e1w <= e2 by thEvTrans;
    then D4: e1w <= e2w by B1,D2;
    DS is consistent;
    then DS is rw-ordered;
    hence contradiction by B1,D2,A1,D3,D4;
  end;
  C2: not e2 << e2w by B1,ORDERS_2:def 6;
  e1 << e2w & e2w << e2 & e2w writesto x,a2
    by thLinPreordEvents,JJ0,A1,C1,C2,B1;
  hence thesis by B1;
end;
