reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem
  Gen w,y implies u,v,u,v are_DTr_wrt w,y
by Lm6,ANALOAF:8;
