reserve P,P1,P2 for Instruction-Sequence of SCM+FSA;

theorem Th11:
 for s being State of SCM+FSA,
     I,J being parahalting really-closed MacroInstruction of SCM+FSA,
  a being read-write Int-Location
 holds if=0(a,I,J) is parahalting &
    (s.a = 0 implies
      IExec(if=0(a,I,J),P,s)
       = IExec(I,P,s) +* Start-At( (card I + card J + 3),SCM+FSA)) &
    (s.a <> 0 implies
      IExec(if=0(a,I,J),P,s)
       = IExec(J,P,s) +* Start-At((card I + card J + 3),SCM+FSA))
proof
  let s be State of SCM+FSA;
  let I,J be parahalting really-closed MacroInstruction of SCM+FSA;
  let a be read-write Int-Location;
A1: I is_halting_on Initialized s,P by SCMFSA7B:19;
  for s being 0-started State of SCM+FSA
  for P being Instruction-Sequence of SCM+FSA
   st if=0(a,I,J) c= P
  holds P halts_on s
  proof
    let s be 0-started State of SCM+FSA;
    Start-At(0,SCM+FSA) c= s by MEMSTR_0:29;
    then
A2: s = Initialize s by FUNCT_4:98;
    let Q be Instruction-Sequence of SCM+FSA
    such that
A3:  if=0(a,I,J) c= Q;
A4:  if=0(a,I,J) c= Q by A3;
A5: I is_halting_on s,Q by SCMFSA7B:19;
A6: J is_halting_on s,Q by SCMFSA7B:19;
A7:  Q +* if=0(a,I,J) = Q by A4,FUNCT_4:98;
    per cases;
    suppose
    s.a = 0;
      then if=0(a,I,J) is_halting_on s,Q by A5,Th7;
      hence Q halts_on s by A2,A7,SCMFSA7B:def 7;
    end;
    suppose
      s.a <> 0;
      then if=0(a,I,J) is_halting_on s,Q by A6,Th9;
      hence Q halts_on s by A2,A7,SCMFSA7B:def 7;
    end;
  end;
  hence if=0(a,I,J) is parahalting by AMISTD_1:def 11;
  thus s.a = 0 implies IExec(if=0(a,I,J),P,s)
   = IExec(I,P,s) +* Start-At(card I + card J + 3,SCM+FSA)
     by A1,Th8;
   J is_halting_on Initialized s,P by SCMFSA7B:19;
  hence thesis by Th10;
end;
