reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th18:
  Gen w,y & v1,u,u,v2 are_DTr_wrt w,y implies v1=u & u=v2
proof
  assume that
A1: Gen w,y and
A2: v1,u,u,v2 are_DTr_wrt w,y;
  set a=v1#u, b=u#v2;
A3: v1,u,a,b are_Ort_wrt w,y by A2;
A4: u,v2,a,b are_Ort_wrt w,y by A2;
A5: v1,u // u,v2 by A2;
  per cases;
  suppose
    v1 = v2;
    hence thesis by A2,Th17;
  end;
  suppose
    v1<>v2;
    then
A6: a<>b by Th7;
    u,v2 // u,b by Th12;
    then
A7: u,v2 '||' u,b;
A8: a,u // u,b by A5,Th13;
    then u,b // a,b by Lm1;
    then
A9: u,b '||' a,b;
A10: u=v2
    proof
      assume
A11:  u<>v2;
A12:  u<>b
      proof
        assume u=b;
        then u#v2=u#u;
        hence contradiction by A11,Th7;
      end;
      u,b,a,b are_Ort_wrt w,y by A1,A4,A7,A11,Lm10;
      then u,b,u,b are_Ort_wrt w, y by A1,A6,A9,Lm10;
      hence contradiction by A1,A12,Lm8;
    end;
    v1,u // a,u by Th12;
    then
A13: v1,u '||' a,u;
    a,u // a,b by A8,Lm1;
    then
A14: a,u '||' a,b;
    v1=u
    proof
      assume
A15:  v1<>u;
A16:  u<>a
      proof
        assume u=a;
        then v1#u=u#u;
        hence contradiction by A15,Th7;
      end;
      a,u,a,b are_Ort_wrt w,y by A1,A3,A13,A15,Lm10;
      then a,u,a,u are_Ort_wrt w, y by A1,A6,A14,Lm10;
      hence contradiction by A1,A16,Lm8;
    end;
    hence thesis by A10;
  end;
end;
