reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th20:
  Gen w,y implies ex t being VECTOR of V st (u,v,u1,t are_DTr_wrt
  w,y or u,v,t,u1 are_DTr_wrt w,y)
proof
  assume
A1: Gen w,y;
  set a=u#v;
  per cases;
  suppose
A2: u=v;
A3: u1,u1,u#u,u1#u1 are_Ort_wrt w,y by A1,Lm5,Lm6;
    u,u // u1,u1 & u,u,u#u,u1#u1 are_Ort_wrt w,y by A1,Lm5,Lm6,ANALOAF:9;
    then u,u,u1,u1 are_DTr_wrt w,y by A3;
    hence thesis by A2;
  end;
  suppose
A4: u<>v;
    a<>u
    proof
      assume a=u;
      then u#u = u#v;
      hence contradiction by A4,Th7;
    end;
    then u-a<>0.V by RLVECT_1:21;
    then consider r being Real such that
A5: (u1-a)-r*(u-a),u-a are_Ort_wrt w,y by A1,ANALMETR:13;
    set b = u1-r*(u-a);
    set t = 2*b-u1;
    u1+t = (1+1)*b by RLSUB_2:61
      .= 1*b+1*b by RLVECT_1:def 6
      .= b+1*b by RLVECT_1:def 8
      .= b+b by RLVECT_1:def 8;
    then
A6: u1#t = b by Def2;
    u1-b = (u1-u1)+r*(u-a) by RLVECT_1:29
      .= 0.V + r*(u-a) by RLVECT_1:15
      .= r*(u-a) by RLVECT_1:4;
    then
A7: u1-t = 2*(r*(u-a)) by A6,Th10
      .= (2*r)*(u-a) by RLVECT_1:def 7;
A8: u1-(a+r*(u-a)) = (u1-r*(u-a))-a by RLVECT_1:27;
    then b-a,u-a are_Ort_wrt w,y by A5,RLVECT_1:27;
    then b-a,u1-t are_Ort_wrt w,y by A7,ANALMETR:7;
    then
A9: a,b,t,u1 are_Ort_wrt w,y by ANALMETR:def 3;
    then
A10: t,u1,u#v,t#u1 are_Ort_wrt w,y by A6,Lm5;
A11: u-v = 2*(u-u#v) by Th10;
    then u1-t = r*(u-v) by A7,RLVECT_1:def 7;
    then r*(u-v) = 1*(u1-t) by RLVECT_1:def 8;
    then v,u // t,u1 or v,u // u1,t by ANALMETR:14;
    then
A12: u,v // u1,t or u,v // t,u1 by ANALOAF:12;
    a,b,u1,t are_Ort_wrt w,y by A9,Lm4;
    then
A13: u1,t,u#v,u1#t are_Ort_wrt w,y by A6,Lm5;
    b-a = (u1-a)-r*(u-a) by A8,RLVECT_1:27;
    then b-a,u-v are_Ort_wrt w,y by A5,A11,ANALMETR:7;
    then a,b,v,u are_Ort_wrt w,y by ANALMETR:def 3;
    then a,b,u,v are_Ort_wrt w,y by Lm4;
    then u,v,u#v,u1#t are_Ort_wrt w,y by A6,Lm5;
    then u,v,u1,t are_DTr_wrt w,y or u,v,t,u1 are_DTr_wrt w,y by A13,A10,A12;
    hence thesis;
  end;
end;
