reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th22:
  u,v,u1,v1 are_DTr_wrt w,y implies v,u,v1,u1 are_DTr_wrt w,y
proof
  assume
A1: u,v,u1,v1 are_DTr_wrt w,y;
  then u,v // u1,v1;
  then
A2: v,u // v1,u1 by ANALOAF:12;
A3: now
    let u,u9,v,v9 be VECTOR of V;
    assume u,u9,v,v9 are_Ort_wrt w,y;
    then v,v9,u,u9 are_Ort_wrt w,y by Lm5;
    then v,v9,u9,u are_Ort_wrt w,y by Lm4;
    hence u9,u,v,v9 are_Ort_wrt w,y by Lm5;
  end;
  u1,v1,u#v,u1#v1 are_Ort_wrt w,y by A1;
  then
A4: v1,u1,v#u,v1#u1 are_Ort_wrt w,y by A3;
  u,v,u#v,u1#v1 are_Ort_wrt w,y by A1;
  then v,u,v#u,v1#u1 are_Ort_wrt w,y by A3;
  hence thesis by A2,A4;
end;
