reserve p,p1,p2,h for Instruction-Sequence of SCM+FSA;
reserve k, l, n for Nat,
  j for Integer,
  i,i1 for Instruction of SCM+FSA;
reserve s, s1, s2 for State of SCM+FSA,
  a for read-write Int-Location,
  b for Int-Location,
  I, J for MacroInstruction of SCM+FSA,
  Ig for good MacroInstruction of SCM+FSA,
  i, j, k, m, n for Nat;

theorem :: IE_while_ne0:
  s.intloc 0 = 1 & s.a <> 0 implies DataPart IExec(while=0(a,I),p,s) =
  DataPart s
proof
  set Ins = NAT;
  assume that
A1: s.intloc 0 = 1 and
A2: s.a <> 0;
  set WH = while=0(a, I);
  set Is = Initialized s, pds = p +* WH;
A3: while=0(a,I) c= pds by FUNCT_4:25;
A4: Is = Initialize Is by MEMSTR_0:44;
  Is.a = s.a by SCMFSA_M:37;
  then WH is_halting_on Is,p by A2,SCMFSA_9:18;
  then
A5: pds halts_on Is by A4,SCMFSA7B:def 7;
A6: Is.a = s.a by SCMFSA_M:37;
  thus DataPart IExec(WH,p,s)
     = DataPart Result(p +* WH,Initialized s) by SCMFSA6B:def 1
    .= DataPart Comput(pds,Is,LifeSpan(pds,Is)) by A5,EXTPRO_1:23
    .= DataPart Initialized s by A2,A6,Th16,A3
    .= DataPart s by A1,SCMFSA_M:19;
end;
