reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th23:
  Gen w,y & v,u1,v,u2 are_DTr_wrt w,y implies u1=u2
proof
  assume that
A1: Gen w,y and
A2: v,u1,v,u2 are_DTr_wrt w,y;
A3: v,u1,v#u1,v#u2 are_Ort_wrt w,y by A2;
A4: v,u2,v#u1,v#u2 are_Ort_wrt w,y by A2;
  v,u1 // v,u1 by ANALOAF:8;
  then
A5: v,u1 '||' v,u1;
  set b=v#u1, c = v#u2;
A6: v,u1 // v,b by Th12;
  then
A7: v,u1 '||' v,b;
A8: v,u1 // v,u2 by A2;
  v,u2 // v,b
  proof
    per cases;
    suppose
      v=b;
      hence thesis by ANALOAF:9;
    end;
    suppose
      v<>b;
      then v<>u1;
      hence thesis by A8,A6,ANALOAF:11;
    end;
  end;
  then
A9: v,u2 '||' v,b;
  v,u2 // v,v by ANALOAF:9;
  then
A10: v,u2 '||' v,v;
A11: v,u2 // v,c by Th12;
  then
A12: v,u2 '||' v,c;
A13: v,u2 // v,u1 by A8,ANALOAF:12;
  v,u1 // v,c
  proof
    per cases;
    suppose
      v=c;
      hence thesis by ANALOAF:9;
    end;
    suppose
      v<>c;
      then v<>u2;
      hence thesis by A13,A11,ANALOAF:11;
    end;
  end;
  then
A14: v,u1 '||' v,c;
  v,u2 // v,u2 by ANALOAF:8;
  then
A15: v,u2 '||' v,u2;
  v,u1 // v,v by ANALOAF:9;
  then
A16: v,u1 '||' v,v;
  assume
A17: u1<>u2;
  per cases by A17;
  suppose
A18: v<>u1;
    then v,u1 '||' b,c by A1,A7,A5,A16,A14,Lm11;
    then b,c,b,c are_Ort_wrt w,y by A1,A3,A18,Lm10;
    hence thesis by A1,A17,Lm8,Th7;
  end;
  suppose
A19: v<>u2;
    then v,u2 '||' b,c by A1,A12,A15,A10,A9,Lm11;
    then b,c,b,c are_Ort_wrt w,y by A1,A4,A19,Lm10;
    hence thesis by A1,A17,Lm8,Th7;
  end;
end;
