reserve x,y for set;
reserve i, j, k for Nat;
reserve I,J,K for Element of Segm 9,
  a,a1 for Nat,
  b,b1,c for Element of Data-Locations SCM;
reserve a, b for Data-Location,
  loc for Nat;
reserve I,J,K for Element of Segm 9,
  a,a1 for Nat,
  b,b1,c for Element of Data-Locations SCM,
  da,db for Data-Location;

theorem
  for q being non halt-free finite
      (the InstructionsF of SCM)-valued NAT-defined Function
  for p being q-autonomic non empty FinPartState of SCM, s1, s2
  being State of SCM st  p c= s1 &  p c= s2
  for P1,P2 being Instruction-Sequence of SCM
      st q c= P1 & q c= P2
  for i being Nat, da being
  Data-Location, loc being Nat, I being Instruction of
SCM st I = CurInstr(P1,Comput(P1,s1,i))
 holds I = da>0_goto loc & loc <> (IC Comput(P1,s1,i)) + 1
  implies ( Comput(P1,s1,i).da > 0 iff Comput(P2,s2,i)
  .da > 0)
proof
  let q being non halt-free finite
      (the InstructionsF of SCM)-valued NAT-defined Function;
  let p be q-autonomic non empty FinPartState of SCM,
      s1, s2 be State of SCM such that
A1:  p c= s1 &  p c= s2;
  let P1,P2 be Instruction-Sequence of SCM
  such that
A2: q c= P1 & q c= P2;
  let i be Nat, da be Data-Location, loc be Nat
 , I be Instruction of SCM such that
A3: I = CurInstr(P1,Comput(P1,s1,i));
  set Cs2i1 = Comput(P2,s2,i+1);
  set Cs1i1 = Comput(P1,s1,i+1);
A4: Cs1i1|dom  p = Cs2i1|dom  p by A2,A1,EXTPRO_1:def 10;
  set Cs2i = Comput(P2,s2,i);
  set Cs1i = Comput(P1,s1,i);
A5: Cs1i1 = Following(P1,Cs1i) by EXTPRO_1:3
    .= Exec (CurInstr(P1,Cs1i), Cs1i);
   IC SCM in dom p by AMISTD_5:6;
   then
A6: (Cs1i1|dom  p).IC SCM = IC Cs1i1 &
    (Cs2i1|dom  p).IC SCM = IC Cs2i1 by FUNCT_1:49;
A7: Cs2i1 = Following(P2,Cs2i) by EXTPRO_1:3
    .= Exec (CurInstr(P2,Cs2i), Cs2i);
  assume that
A8: I = da>0_goto loc and
A9: loc <> (IC Comput(P1,s1,i)) + 1;
A10: I = CurInstr(P2,Comput(P2,s2,i)) by A3,A2,A1,AMISTD_5:7;
A11: now
    assume that
A12: Comput(P2,s2,i).da > 0 and
A13: Comput(P1,s1,i).da <= 0;
    Cs2i1.IC SCM = loc by A10,A7,A8,A12,AMI_3:9;
    hence contradiction by A3,A5,A6,A4,A8,A9,A13,AMI_3:9;
  end;
A14: IC Cs1i = IC Cs2i by A2,A1,AMISTD_5:7;
  now
    assume that
A15: Comput(P1,s1,i).da > 0 and
A16: Comput(P2,s2,i).da <= 0;
    Cs1i1.IC SCM = loc by A3,A5,A8,A15,AMI_3:9;
    hence contradiction by A14,A10,A7,A6,A4,A8,A9,A16,AMI_3:9;
  end;
  hence thesis by A11;
end;
