reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th24:
  Gen w,y & u,v,u1,v1 are_DTr_wrt w,y & u,v,u1,v2 are_DTr_wrt w,y
  implies (u=v or v1=v2)
proof
  assume that
A1: Gen w,y and
A2: u,v,u1,v1 are_DTr_wrt w,y & u,v,u1,v2 are_DTr_wrt w,y;
  assume u<>v;
  then u1,v1,u1,v2 are_DTr_wrt w,y by A1,A2,Th19;
  hence thesis by A1,Th23;
end;
