reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th25:
  Gen w,y & u<>u1 & u,u1,v,v1 are_DTr_wrt w,y & (u,u1,v,v2
  are_DTr_wrt w,y or u,u1,v2,v are_DTr_wrt w,y) implies v1=v2
proof
  assume that
A1: Gen w,y and
A2: u<>u1 & u,u1,v,v1 are_DTr_wrt w,y and
A3: u,u1,v,v2 are_DTr_wrt w,y or u,u1,v2,v are_DTr_wrt w,y;
  now
    assume u,u1,v2,v are_DTr_wrt w,y;
    then
A4: v2,v,v,v1 are_DTr_wrt w,y by A1,A2,Th19;
    then v=v2 by A1,Th18;
    hence thesis by A1,A4,Th18;
  end;
  hence thesis by A1,A2,A3,Th24;
end;
