reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th26:
  Gen w,y & u,v,u1,v1 are_DTr_wrt w,y implies u,v,(u#u1),(v#v1) are_DTr_wrt w,y
proof
  assume that
A1: Gen w,y and
A2: u,v,u1,v1 are_DTr_wrt w,y;
  set p=u#u1,q=v#v1,r=u#v,s=u1#v1;
A3: u=v & u1=v1 implies p,q,r,(p#q) are_Ort_wrt w,y by A1,Lm9;
  p#q = r#s by Th6;
  then r,s // r,p#q by Th12;
  then
A4: r,s '||' r,p#q;
  u,v,r,s are_Ort_wrt w,y & u1,v1,r,s are_Ort_wrt w,y by A2;
  then
A5: r<>s implies u1,v1,r,(p#q) are_Ort_wrt w,y & u,v,r,(p#q) are_Ort_wrt w,
  y by A1,A4,Lm10;
A6: now
    assume r=s;
    then r=r#s .= p#q by Th6;
    hence u1,v1,r,(p#q) are_Ort_wrt w,y & u,v,r,(p#q) are_Ort_wrt w,y by A1,Lm9
;
  end;
A7: u,v // u1,v1 by A2;
  then u1,v1 // u,v by ANALOAF:12;
  then u1,v1 // (u1#u),(v1#v) by Th14;
  then u1,v1 '||' p,q;
  then
A8: u=v & u1<>v1 implies p,q,r,(p#q) are_Ort_wrt w,y by A1,A6,A5,Lm10;
A9: u,v // (u#u1),(v#v1) by A7,Th14;
  then u,v '||' p,q;
  then u<>v implies p,q,r,(p#q) are_Ort_wrt w,y by A1,A6,A5,Lm10;
  hence thesis by A9,A6,A5,A8,A3;
end;
