reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th27:
  Gen w,y & u,v,u1,v1 are_DTr_wrt w,y implies (u,v,(u#v1),(v#u1)
  are_DTr_wrt w,y or u,v,(v#u1),(u#v1) are_DTr_wrt w,y)
proof
  assume that
A1: Gen w,y and
A2: u,v,u1,v1 are_DTr_wrt w,y;
  set p=u#v1,q=v#u1,r=u#v,s=u1#v1;
A3: u,v,r,s are_Ort_wrt w,y by A2;
A4: p#q = r#s by Th6;
  then r,s // r,p#q by Th12;
  then
A5: r,s '||' r,p#q;
  u,v // u1,v1 by A2;
  then
A6: u,v '||' p,q by Lm2;
  then
A7: u,v // p,q or u,v // q,p;
  per cases;
  suppose
    u=v;
    hence thesis by A1,A2,Th26;
  end;
  suppose that
A8: u<>v;
    per cases;
    suppose
A9:   r=s;
      then
A10:  q,p,r,(q#p) are_Ort_wrt w,y by A1,A4,Lm9;
      u,v,r,(p#q) are_Ort_wrt w,y & p,q,r,(p#q) are_Ort_wrt w,y by A1,A4,A9,Lm9
;
      hence thesis by A7,A10;
    end;
    suppose
      r<>s;
      then
A11:  u,v,r,(p#q) are_Ort_wrt w,y by A1,A3,A5,Lm10;
      then r,(p#q),p,q are_Ort_wrt w,y by A1,A6,A8,Lm10;
      then r,(p#q),q,p are_Ort_wrt w,y by Lm4;
      then
A12:  q,p,r,(q#p) are_Ort_wrt w,y by Lm5;
      p,q,r,(p#q) are_Ort_wrt w,y by A1,A6,A8,A11,Lm10;
      hence thesis by A7,A11,A12;
    end;
  end;
end;
