
theorem Th38:
  for am,bm,cm,dm being non pair set for cin being set st cin <> [
<*dm,GFA3AdderOutput(am,bm,cm)*>,nor2] & not cin in InnerVertices BitGFA3Str(
am,bm,cm) for s being State of BitFTA3Circ(am,bm,cm,dm,cin) for a1,a2,a3,a4,a5
being Element of BOOLEAN st a1 = s.am & a2 = s.bm & a3 = s.cm & a4 = s.dm & a5
= s.cin holds Following(s,2).GFA3AdderOutput(am,bm,cm) = 'not' ('not' a1 'xor'
  'not' a2 'xor' 'not' a3) & Following(s,2).am = a1 & Following(s,2).bm = a2 &
  Following(s,2).cm = a3 & Following(s,2).dm = a4 & Following(s,2).cin = a5
proof
  let am,bm,cm,dm be non pair set;
  let cin be set such that
A1: cin <> [<*dm,GFA3AdderOutput(am,bm,cm)*>,nor2] & not cin in
  InnerVertices BitGFA3Str(am,bm,cm);
  set A1 = GFA3AdderOutput(am,bm,cm);
  set C1 = BitGFA3Circ(am,bm,cm);
  set S1 = BitGFA3Str(am,bm,cm);
  set S2 = BitGFA3Str(A1,cin,dm);
  set C2 = BitGFA3Circ(A1,cin,dm);
  set S = BitFTA3Str(am,bm,cm,dm,cin);
  let s be State of BitFTA3Circ(am,bm,cm,dm,cin);
  let a1,a2,a3,a4,a5 be Element of BOOLEAN such that
A2: a1 = s.am and
A3: a2 = s.bm and
A4: a3 = s.cm and
A5: a4 = s.dm and
A6: a5 = s.cin;
  reconsider s1 = s|the carrier of S1 as State of C1 by FACIRC_1:26;
A7: dom s1 = the carrier of S1 by CIRCUIT1:3;
A8: dm in InputVertices S by A1,Th36;
  then
A9: (Following s).dm = a4 by A5,CIRCUIT2:def 5;
A10: cm in InputVertices S by A1,Th36;
  then
A11: (Following s).cm = a3 by A4,CIRCUIT2:def 5;
  bm in the carrier of S1 by GFACIRC1:132;
  then
A12: a2 = s1.bm by A3,A7,FUNCT_1:47;
  reconsider t = s as State of C1+*C2;
  A1 in the carrier of S1 & InputVertices S1 misses InnerVertices S2 by Lm32,
GFACIRC1:132;
  then
A13: Following(t,2).GFA3AdderOutput(am,bm,cm) = Following(s1,2).
  GFA3AdderOutput(am,bm,cm) by FACIRC_1:32;
  cm in the carrier of S1 by GFACIRC1:132;
  then
A14: a3 = s1.cm by A4,A7,FUNCT_1:47;
  am in the carrier of S1 by GFACIRC1:132;
  then a1 = s1.am by A2,A7,FUNCT_1:47;
  hence Following(s,2).GFA3AdderOutput(am,bm,cm) = 'not' ('not' a1 'xor' 'not'
  a2 'xor' 'not' a3) by A12,A14,A13,GFACIRC1:135;
A15: bm in InputVertices S by A1,Th36;
  then
A16: (Following s).bm = a2 by A3,CIRCUIT2:def 5;
A17: cin in InputVertices S by A1,Th36;
  then
A18: (Following s).cin = a5 by A6,CIRCUIT2:def 5;
A19: am in InputVertices S by A1,Th36;
  then Following(s,2) = Following Following s & (Following s).am = a1 by A2,
CIRCUIT2:def 5,FACIRC_1:15;
  hence thesis by A19,A15,A10,A8,A17,A16,A11,A9,A18,CIRCUIT2:def 5;
end;
