reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th41:
  for u,u9,u1,u2,v1,v2,t1,t2,w1,w2 being VECTOR of V holds (Gen w,
y & u<>u9 & u,u9,u1,t1 are_DTr_wrt w,y & u,u9,u2,t2 are_DTr_wrt w,y & u,u9,v1,
  w1 are_DTr_wrt w,y & u,u9,v2,w2 are_DTr_wrt w,y & u1,u2,v1,v2 are_DTr_wrt w,y
  implies t1,t2,w1,w2 are_DTr_wrt w,y)
proof
  let u,u9,u1,u2,v1,v2,t1,t2,w1,w2 be VECTOR of V;
  assume that
A1: Gen w,y & u<>u9 and
A2: u,u9,u1,t1 are_DTr_wrt w,y & u,u9,u2,t2 are_DTr_wrt w,y and
A3: u,u9,v1,w1 are_DTr_wrt w,y & u,u9,v2,w2 are_DTr_wrt w,y and
A4: u1,u2,v1,v2 are_DTr_wrt w,y;
  set uu=u1#u2,vv=v1#v2;
A5: u,u9,uu,(t1#t2) are_DTr_wrt w,y & u,u9,vv,(w1#w2) are_DTr_wrt w,y by A1,A2
,A3,Th39;
  v1,v2,uu,vv are_Ort_wrt w,y by A4;
  then
A6: w1,w2,t1#t2,w1#w2 are_Ort_wrt w,y by A1,A3,A5,Th40;
  u1,u2,uu,vv are_Ort_wrt w,y by A4;
  then
A7: t1,t2,t1#t2,w1#w2 are_Ort_wrt w,y by A1,A2,A5,Th40;
  u1,u2 // v1,v2 by A4;
  then t1,t2 // w1,w2 by A1,A2,A3,Th37;
  hence thesis by A7,A6;
end;
