reserve P,Q for Instruction-Sequence of SCM+FSA;
reserve m, n for Nat;
reserve f for FinSeq-Location,
  c for Int-Location;
reserve s for State of SCM+FSA,
  I for MacroInstruction of SCM+FSA,
  a for read-write Int-Location;
reserve i,k,m,n for Nat;
reserve s for State of SCM+FSA,
  I for MacroInstruction of SCM+FSA,
  a for read-write Int-Location;

theorem Th18:
  for I being MacroInstruction of SCM+FSA,a being read-write Int-Location,
s being State of SCM+FSA,k,n being Nat
 st IC StepWhile>0(a,I,P,s).k =
   0 & StepWhile>0(a,I,P,s).k= Comput(P +* while>0(a,I),
   (Initialize s),n)
 holds StepWhile>0(a,I,P,s).k = Initialize(StepWhile>0(a,I,P,s).k)
  & StepWhile>0(a,I,P,s).(k+1)=
Comput(P +* while>0(a,I), Initialize s,
   n +(LifeSpan(P +* while>0(a,I) +* I,Initialize(StepWhile>0(a,I,P,s).k)
  ) + 2))
proof
  let I be MacroInstruction of SCM+FSA,a be read-write Int-Location,
      s be State of SCM+FSA,k,n be Nat;
  set D = Int-Locations \/ FinSeq-Locations;
  set s1 = Initialize s,
      P1 = P +* while>0(a,I);
  set sk=StepWhile>0(a,I,P,s).k;
  set s2=Initialize sk;
  assume
A1: IC sk = 0;
  assume
A2: sk = Comput(P1, s1,n);
   sk is 0-started by A1;
   then Start-At(0,SCM+FSA) c= sk by MEMSTR_0:29;
  hence s2=sk by FUNCT_4:98;
  hence
  StepWhile>0(a,I,P,s).(k+1)=
   Comput(P1, sk,LifeSpan(P +* while>0(a,I) +* I,
   Initialize sk) +2)
   by Def2
   .= Comput(P1, s1,n +(LifeSpan(P +* while>0(a,I) +* I,
   Initialize sk) + 2))
        by A2,EXTPRO_1:4;
end;
