reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th5:
  Gen w,y implies for u,v holds u,0.V are_Ort_wrt w,y & 0.V,v are_Ort_wrt w,y
proof
  assume
A1: Gen w,y;
  let u,v;
  consider a1,a2 such that
A2: u = a1*w + a2*y by A1;
  consider b1,b2 such that
A3: v = b1*w + b2*y by A1;
A4: 0.V = 0.V + 0.V by RLVECT_1:4
    .= 0*w + 0.V by RLVECT_1:10
    .= 0*w + 0*y by RLVECT_1:10;
  a1*0 + a2*0 = 0;
  hence u,0.V are_Ort_wrt w,y by A2,A4;
  0*b1 + 0*b2 = 0;
  hence thesis by A3,A4;
end;
