
theorem
  for S1,S2 being unsplit gate`1=arity gate`2isBoolean non void non
empty ManySortedSign for A1 being Boolean gate`2=den Circuit of S1 for A2 being
Boolean gate`2=den Circuit of S2 for s being State of A1+*A2, v being Vertex of
  S1+*S2 holds (for s1 being State of A1 st s1 = s|the carrier of S1 holds v in
InnerVertices S1 or v in the carrier of S1 & v in InputVertices(S1+*S2) implies
  (Following s).v = (Following s1).v) & for s2 being State of A2 st s2 = s|the
  carrier of S2 holds v in InnerVertices S2 or v in the carrier of S2 & v in
  InputVertices(S1+*S2) implies (Following s).v = (Following s2).v
proof
  let S1,S2 be unsplit gate`1=arity gate`2isBoolean non void non empty
  ManySortedSign;
  let A1 be Boolean gate`2=den Circuit of S1;
  let A2 be Boolean gate`2=den Circuit of S2;
  A1 tolerates A2 by Th60;
  hence thesis by Th31;
end;
