reserve V for RealLinearSpace;
reserve u,u1,u2,v,v1,v2,w,w1,y for VECTOR of V;
reserve a,a1,a2,b,b1,b2,c1,c2 for Real;
reserve x,z for set;

theorem Th8:
  Gen w,y implies for u ex v st u,v are_Ort_wrt w,y & v<>0.V
proof
  assume
A1: Gen w,y;
  let u;
  consider a1,a2 such that
A2: u = a1*w + a2*y by A1;
A3: now
    set v = a2*w + (-a1)*y;
    assume
A4: u<>0.V;
    take v;
    a1*a2 + a2*(-a1) = 0;
    hence u,v are_Ort_wrt w,y by A2;
    v<>0.V
    proof
      assume v=0.V;
      then a2 = 0 & -a1 = 0 by A1;
      then u = 0*w + 0.V by A2,RLVECT_1:10
        .= 0*w by RLVECT_1:4
        .= 0.V by RLVECT_1:10;
      hence contradiction by A4;
    end;
    hence v<>0.V;
  end;
  now
    assume
A5: u = 0.V;
    take v=w;
    thus u,v are_Ort_wrt w,y by A1,A5,Th5;
    thus v<>0.V by A1,Lm5;
  end;
  hence thesis by A3;
end;
