reserve s for State of SCM+FSA,
  I for MacroInstruction of SCM+FSA,
  a for read-write Int-Location;
reserve i,j,k,n for Nat;
reserve P,P1,P2,Q for Instruction-Sequence of SCM+FSA;

theorem Th4:
  for s being State of SCM+FSA,
      I being really-closed MacroInstruction of SCM+FSA,
      a being read-write Int-Location st I is_halting_onInit s,P & s.a >0 holds
   IC Comput(P +* while>0(a,I),Initialized s,
    LifeSpan(P +* I,Initialized s) + 2) =  0 &
for k being Nat
 st k <= LifeSpan(P +* I,Initialized s) + 2
 holds IC Comput(P +* while>0(a,I),Initialized s,k) in dom while>0(a,I)
proof
  let s be State of SCM+FSA,I be really-closed MacroInstruction of SCM+FSA;
  let a be read-write Int-Location;
  set s0=Initialized s, sw = Initialized s,
      Pw = P +* while>0(a,I), PI = P +* I,
      s0I= Initialize s0;
A1: sw=s0I by MEMSTR_0:44;
  assume I is_halting_onInit s,P;
  then
A2: I is_halting_on s0,P by SCM_HALT:31;
  assume s.a >0;
  then
A3: s0.a>0 by SCMFSA_M:37;
  hence IC Comput(Pw, sw,LifeSpan(PI,sw) + 2) =  0
          by A2,A1,SCMFSA_9:42;
  thus thesis by A2,A3,A1,SCMFSA_9:42;
end;
