theorem Th44:
  u=a & v=b & u1=a1 & v1=b1 implies (a,b // a1,b1 iff u,v,u1,v1
  are_DTr_wrt w,y)
proof
  assume
A1: u=a & v=b & u1=a1 & v1=b1;
  hereby
    assume a,b // a1,b1;
    then [[a,b],[a1,b1]] in DTrapezium(V,w,y) by ANALOAF:def 2;
    hence u,v,u1,v1 are_DTr_wrt w,y by A1,Th42;
  end;
  assume u,v,u1,v1 are_DTr_wrt w,y;
  then [[a,b],[a1,b1]] in DTrapezium(V,w,y) by A1,Th42;
  hence a,b // a1,b1 by ANALOAF:def 2;
end;
