theorem Th52:
  C1, C2 are_similar_wrt f, g implies f.:InputVertices G1 = InputVertices G2 &
  f.:InnerVertices G1 = InnerVertices G2
proof
  assume C1, C2 are_similar_wrt f, g;
  then G1, G2 are_equivalent_wrt f, g by Th36;
  hence thesis by Th28;
end;
